TI Obsoletes FPGA
Athena Security IPs Designed to Mend Holes in SoCs
Last Man on Earth: How Would You Behave?
Channel Consolidation & Conflict: Back to the Future!
Is Formal Verification Artificial Intelligence?
S2C SETS NEW STANDARDS FOR FPGA-BASED PROTOTYPING WITH PRODIGY COMPLETE PROTOTYPING PLATFORM
"IP @ DAC: Design reuse still not for faint of heart" by Peggy Aycinena
How can Verification IPs Help the SoC Testing Process? by Kamil Rymarz
“Thursday is Training Day” at the 52nd Design Automation Conference
"Analysis of Clock Intent Requires Smarter SoC Verification" by Sarath Kirihennedige
EdXact News (detailed articles open at bottom)
EdXact at CDN Live EMEA 2015!
EdXact Participates at SNUG 2015 Designer Community Expo
EdXact Participates at CDNLIVE Silicon Valley 2015
EdXact Exhibits at Synopsys SIG Meeting, hosted at DesignCon
EdXact delivers version 1.9 of Alps, Viso, Belledonne
EdXact delivers new versions of Alps, Viso, Belledonne and Brenner
Version 5.5 of Jivaro is getting delivered
EdXact demonstrates Unique Capabilities for FinFet and TriGate Support at DAC
EdXact and Oasic to present flow prototype at edaWorkshop14 in Hanover, Germany
Version 1.7 of Belledonne is ready!
Meet us ...
Cadence Live User Group Meeting - April 27-28 2015 [Munich, Germany]
Design Automation Conference - June 7-11 2015 [San Francisco, USA]
Grand Technology Seminar - July 2015 [Hsinchu, Taiwan]
Cadence Live Boston - September 2 2015 [Boston, USA]
Synopsys HSPICE SIG at DesignCon - Jan 28 2015 [Santa Clara, USA]
Cadence Live Silicon Valley - March 10-11 2015 [Santa Clara, USA]
Synopsys SNUG Silicon Valley - March 23-25 2015 [Santa Clara, USA]
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