News

14.06.10: [EN] TSMC Selected EdXact Jivaro for 28nm Analog and Mixed-Signal Reference Flow  <here>

24.05.10: [EN] EdXact To Enhance Interactive Debugging Capabilities, Hierarchical File Handling and Improved Selectivity Features to Its Post-Layout Analysis Tools at DAC  <here>

25.01.10: [EN] MediaTek Deploys EdXact’s Jivaro Technology for Analog Circuits  <here>

More and coverage <here>

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EDXACT's Jivaro(TM) technology and derived tools are the booster of all existing simulation and analysis tools in advanced nanometer design flows.

Whether you run advanced RF simulation,
or mixed-signal simulations with spice accuracy,
or you simply exploit the interconnect parasitics for timing or crosstalk verification -

whether you use a spice simulator or a fast-spice one:

Backannotating interconnect modeling (parasitics) into any simulation adds a level of complexity to the simulator, it simply cannot cope with due to the number and complexity of the parasitic resistors, capacitors, inductors and coupling via the electric and magnetic field.



EDXACT is concentrating on remodeling the parasitics in a controlled way. The approach is unique and compatible with all existing flows. Industry leaders testify their experiences voluntarily.

Using the JIVARO(TM) technology, you'll have three major experiences:

1. You do not change your existing flow, JIVARO(TM) technology integrates naturally.

2. The performance of your existing extraction and simulation infrastructure is getting much better.

3. You keep the accuracy from extraction down to the simulation without tricks.