Whitepapers and literature

[EN] "Path resistance extraction for full-chip latchup verification."

[EN] "Extraction and Analysis of Metal Interconnects in Power MOS Devices with Tool: Comanche"

[EN] "How do you qualify netlist reduction and circuit extraction?"

[EN] "Analogue Behavioural Modelling for Electronic Circuits"

[EN] "Rapid Inductance Modeling and Netlist Reduction Boosts RFIC design"

[FR] "Comment simuler rapidement les inductances des circuits RF"

[DE] "Integrierte Spiralinduktivitäten für Hochfrequenz IC unter Ausnutzung von RLCK Modellreduzierung"

[EN] "Spiral inductor modeling for RFIC using RLCK model order reduction"

[EN] "Parasitics Move Model Order Reduction into Electronic Design Automation"

[EN] 2A704: Robust design for efficient use of nanometre technologies (ROBIN)