Viso – Parasitics-centric analysis

Enables quick analysis of interconnect parasitics in order to pinpoint problems. Allows timing estimation and accurate comparison of different extracted netlists. Integrated into all major design flows. Request data sheets

 

 

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At 90nm and below, parasitics on the interconnections crucially impact circuit behavior. Their analysis is getting extremely important, since they impact gain, delay, maximum clock rate, cross-coupling, level of ESD protection and other features, which can run a chip out of specifications or cause it to completely fail.

Parasitics-related problems can be summarized to the following:

•  Intra-Net pin to pin resistance (same net)

•  Intra-Net pin to pin delay (same net)

•  Inter-Net coupling capacitances

•  Inter-Net decoupling capacitances

•  Intra-Net pin to pin S/Y/Z parameters

•  Main current paths between different pins

•  Voltage drop along current paths

•  Electrical fields along current paths

The calculations usually need to be complete, meaning that for instance all effective resistances for all combinations of input and output pins need to be calculated. Today’s simulation tools, whether spice or fast-spice, are swamped with those calculations.

 

New, dedicated tools are necessary to analyze parasitics entirely and in timely manner.

Viso is part of a new family of analysis tools, that carry out analyses on the electrical grid of parasitics. This parasitics-centric approach allows for analysis times that are very short, thus delivering accurate insight into the circuit and its parasitics.

Viso seamlessly integrates into existing design verification flows after the LPE tool (layout parasitics extraction): e.g. Cadence QRC, Mentor Calibre XRC, Synopsys Star RCXT. 

 

Benefits

• Reduces backend verification cycle time
• Improves probability of first silicon success
• Early detection of gross errors
• Increases effectiveness of backend flow: Simulation is launched only when the circuit has successfully passed analysis of interconnects

 

Features

• Viso provides unparalleled netlist analysis capabilities for all types of parasitic netlist components:

          - R, RC, RCC
          - Interconnections, Substrate, Package

• Calculates the following pin to pin information:

           - Intra-Net pin to pin resistance and delay
           - Inter-Net summary of coupling and decoupling capacitances between nets
           - Intra-Net and Inter-Nets pin to pin S/Y/Z parameters

• Detection of SHORTS and OPENS

• Calculations can be performed selectively on certain nets or groups of nets.

• Supports different formats

• Supports the Touchstone output format for S/Y/Z parameters.

• Compatible with major EDA vendor’s backend flows

• Application Programming Interface