Designers using advanced technologies are confronted with several problems at the same time.

1. Very important number of parasitics for post-layout simulation tasks
2. Simulation time of netlists with parasitics rising exponentially with the number of parasitics
3. Rapidly growing memory footprint of simulation with parasitics
4. Each extraction tool, each simulation tool applies its own filtering, reduction or data crunching in order to reduce the number of parasitics. Each of the methods has different advantages and shortcomings.
5. Certain simulations need new tools or other simplifications in order to cope with the sheer complexity
6. While in the middle of a project and using approved design kits and flows, switching between different extraction and simulation tools is very difficult.

EdXact’s solutions help designers cope with those problems.

 

At feature sizes of 90nm and below, parasitics substantially impact the behavior of integrated circuit design.

Parasitics or parasitic elements are the models of unwanted effects, which could be ignored at larger process nodes.

The models are usually linear models, taking advantage of existing model cards of Spice-like simulation tools.

 

Generally, we distinguish the following major contributors:

• Resistors ( R ), for resistive effects on interconnects
• Capacitors ( C ), modelling the electric field between lines and ground potential
• Coupling capacitors ( CC ), modelling the electric field between different lines
• Inductances ( L ), modelling the magnetic self-inductance of lines, spiral inductors and others
• Mutual inductances ( M ), modelling the magnetic coupling between different lines

 

We propose several tools that speed up the overall post-layout verification flow for all design styles:

analog/RF, digital, memory, and mixed-mode.

Jivaro – Industry-leading netlist reduction platform

• Speeds up simulation time, increases  accuracy and, reduces memory footprint.
• Integrated into all major design flows, several graphical user interfaces
• Used in production for memory, mixed-signal, analog, RF flows, timing.
• Many customer references.

 

Viso – Parasitics-centric analysis

• Analysis of interconnects and parasitics of a design
• Parasitic resistance between pins of a net
• Parasitic capacitance between nets
• Static current density and IR drop
• S, Y and Z parameters between pins of a net
• Detection of OPEN and SHORT circuits