Jivaro – Netlist reduction platform.

Speeds up simulation time, increases  accuracy and, reduces memory footprint. Integrated into all major design flows, several graphical user interfaces Used in production for memory, mixed-signal, analog, RF flows, timing. Many customer references. Request data sheets

 

 

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Netlist reduction is applied on netlists of integrated circuits containing large numbers of parasitics. The primary goals of netlist reduction are as follows:

1. Reduce the simulation time

2. Keep the same degree of accuracy

3. Reduce the memory footprint of the simulation tool

4. Reduce memory storage requirements of the netlists

 

 

 

 

 

 

Netlist reduction is an advanced scientific topic. 

Netlist reduction is NOT simply data crunching or filtering, because of the following requirements:

•  Accuracy
•  Stability
•  Passivity
•  Realizability
•  Scalability 
•  Verifiability

 

Jivaro fulfills all of the above.

 

Features

•  Jivaro provides unparalleled netlist reduction capabilities for all types of parasitic netlist components:
  R, RC, RCC, RLC, RLCK, voltage or current controlled sources, substrate, package

•  Jivaro supports all major file formats: DSPF, SPEF, SPICE3, HSPICE, SPECTRE

•  Jivaro works for all design styles (RF, Analog, Mixed-signal, Digital, Memory, etc.)

•  Reduction can be applied differently on selected nets or sub-circuits within the hierarchy

•  Reduction can be applied with additional structure preserving requirements (e.g. EM)

•  Jivaro can be applied to any kind of process

•  Jivaro is used in production with all major EDA vendor’s backend flows