Contents

Jivaro A

Jivaro D

Comanche

VRFJ

Jivaro for GoldenGate

Whitepapers

 

Whitepapers and literature




[EN] "How do you qualify netlist reduction and circuit extraction?"

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[EN] "EDXACT's participation in Synopsys Interoperability Program"
[EN] "EDXACT's participation in Synopsys Interoperability Program"(6 MB)

[EN] "Analogue Behavioural Modelling for Electronic Circuits"

[EN] "Rapid Inductance Modeling and Netlist Reduction Boosts RFIC design"

[FR] "Comment simuler rapidement les inductances des circuits RF"

[DE] "Integrierte Spiralinduktivitäten für Hochfrequenz IC unter Ausnutzung von RLCK Modellreduzierung"

[EN] "Spiral inductor modeling for RFIC using RLCK model order reduction"

[EN] "Parasitics Move Model Order Reduction into Electronic Design Automation"

[EN] 2A704: Robust design for efficient use of nanometre technologies (ROBIN)