General presentation
JIVARO is a tool for the IC nanometer designs dedicated to the reduction of parasitic networks. It helps backend physical verification teams to reduce time to market by enabling and speeding up post layout simulation of huge parasitic extracted circuits, while keeping a very high accuracy.
JIVARO applies new fundamental mathematical approach to perform netlist reduction. The trade-off between accuracy and reduction can be controlled, thanks to the implementation of a whole set of standard and innovative algorithms.
JIVARO has been proven to dramatically accelerate IC simulation while preserving an outstanding accuracy and has already been adopted at leading IDM companies worldwide.
Benefits
Reduces backend verification cycle time
Improves chances for a successful layout
Improves Analysis capacity
Simulation time for larger designs turns from infinite into hours, even minutes
Disk and memory requirements for simulation tools decrease
Features
Jivaro provides unparalleled netlist reduction capabilities for all types of parasitic netlist components:
R, RC, RCC, RLC, RLCK, Voltage or current controlled sources , Substrate, Package
Jivaro supports the following I/O formats:
DSPF, SPEF, SPICE3, HSPICE, SPECTRE
Jivaro works for all design styles (RF, Analog , Mixed-signal, Digital, Memory, etc.)
Reduction can be applied differently on selected nets or sub-circuits within the hierarchy
Reduction can be applied with Electromigration preservation option
Jivaro can be applied to any kind of process: Cmos, BiCmos, GaAs, SOI, etc.
Jivaro is compatible with major EDA vendors backend flows
