General presentation
COMANCHE is a tool for IC nanometer designs dedicated to the exploration and analysis of huge parasitic networks. It helps backend physical verification teams to reduce time to market by quickly and accurately calculating various metrics related to the extracted parasitics. This allows the detection of gross errors on their circuits, early in the verification flow, avoiding time consuming simulations. Based on a new fundamental mathematical approach, COMANCHE is complementary to the JIVARO reduction suite that reduces parasitic networks. It is mostly suited for being used before JIVARO for checking design errors. But it can also be used after the JIVARO reduction for probing reduced parasitic data.
Benefits
Reduces backend verification cycle time
Improves chances for a successful layout
Better design expertise through fast exploration of the parasitic data information
Early detection of gross errors
Simulation is launched only when the circuit has successfully passed interconnections analysis
Features
Provides unparalleled netlist analysis capabilities for all types of parasitic netlist components:
- R, RC, RCC
- Interconnections, Substrate, Package
Calculates the following pin to pin information:
- Intra-Net pin to pin resistance and delay
- Inter-NETs summary of coupling and decoupling capacitances
- Intra-Net and Inter-Nets pin to pin S/Y/Z parameters
Calculations can be performed selectively on certain nets or groups of nets.
Supports the DSPF and SPEF input formats
Supports the Touchstone output format for S/Y/Z parameters.
Compatible with major EDA vendors backend flows
Multi-threading mode
API in Tcl (Perl and Python on demand)
Options
COMANCHE can be delivered with a GUI enabling fast interaction and results display.
