Complexity of Creating Integrated Circuits
Creating integrated circuits is getting more and more difficult due to an enormous demand of integrating more and more functionality in smaller and smaller devices. Designers of integrated circuits find themselves in the middle of an equation with four major parameters:
- complexity
- time to market
- problems due to physics
- tremendous cost of production failures.
One would love to continue to trade-off in any of those direction, but alas, it is not possible.
For cost reasons and performance optimisation latest technologies have to be used. Unfortunately, the sub-100nm technologies are all suffering from DFM issues and backannotated simulation is becoming an extremly difficult task. The following graph shows the number of different electrical problems needing attention. Most of these problems are addressed by extraction tools, simulation tools or specialised analysis engines.
The modeling is usually carried out using lumped resistors, capacitors, inductors, coupling capacitors and mutual inductors. Those parasitics substantially slow down circuit simulation. While a schematic might only take seconds for a small block, an extracted view plus the parasitics modeling the interconnections might already take minutes to hours. Take a larger block or even a full layout, and simulation might not be achieved any more.
The parasitics add a large block of linear network components into the simulation, which even slows down fast-spice simulators by an order of magnitude. The usual and simple solution is to filter away a lot of the parasitics using thresholds. This was possible in the past, when the impact of parasitics was less important. Today, when parasitics play a more important role on delay than the circuit itself, the so-called smart filtering is no viable solution any more. What is needed is technology, that remodels the huge and linear parasitics network without loosing any of the important parts. A sophisticated error control needs to be used.
EDXACT's tools are based on it's TOTEM(TM) parasitics database. The speciality of this database is that it marries the usual network representation with mathematical, matrix- and vector-based methods. Coupled with the database is a huge amount of different algorithms, that can be applied whenever necessary or possible.
Verification Acceleration
Whatever tool you use for netlist extraction, whatever tools you use for circuit simulation, once it comes to parasitics, all are suffering from the same set of problems:
- Parasitic extraction tools generate very quickly enormous amounts of data. Those amounts of data are generated by more and more complex modeling of different effects. Think of vicinity effects, skin effects, dishing, cheesing and many more.
- Circuit simulation tools already suffer from the fact that the netlist of the "designed" circuit is getting enormous. Now that parasitics need to be added, the simulators cannot cope any more. Simulations fail.
- The question who should solve this problem is in between extraction and analysis, therefore extraction nor simulation teams are taking responsibly action to address the topic.
Netlist Reduction
Netlist reduction is the word to be used. A lot of litterature can be found on the topic, very few industrial solutions are provided. As far as we can see, EDXACT is the only company to actively push for accurate, scalable, flexible and mathematics based netlist reduction.
Netlist reduction aims to serve four goals:
Goal1: Reduce the amount of data
Goal2: Reduce the memory footprint
Goal3: Speed up simulation
Goal4: Do not degrade simulation accuracy
Result from numerous tests in different flows from different leading semiconductor houses, testify the following adjectives with respect to the goals and the performance of EDXACT's tools:
Goal 1:
massive
Goal 2:
important
Goal 3:
an order of magnitude
Goal 4:
very accurate and tuneable
Additionally, netlist reduction needs to comply with the following requirements:
Accuracy
Needs to be preserved for DC, AC, any simulation
Requirements are different for different flows
Stability
A stable system must not become unstable
Simulation may blow up if unstable
Passivity
Input system and output system passive elements
R,L,C,K elements do not generate energy
Realizability
Simulator must be able to use the reduced model using standard interfaces
Additional constraints forcing positive circuit components or no controlled current sources
Scalability
Handling of networks with large number of ports
E.g. power nets, substrate models
Verifiability
Possibility to dissociate extraction/simulation from reduction to judge on the different requirements or to turn it on/off.
EDXACT is proud that its technology excels in all different requirements.
Go into the
testimonials section and see what people who actually use the technology say.
